A three-dimensional (3D) chip integration technology can reduce a signal transmission distance and improve system performance. Regarding an electronic device having a regular structure, for example, a memory chip, a memory capacity thereof can be flexibly expanded according to an existing chip fabrication method through the 3D chip integration technology without re-planning a layout and additionally fabricating a new optical mask to meet a memory requirement of new application hardware.
The 3D chip integration technology includes two main types of a 3D packaging technique and a 3D connection technique. Regarding the 3D packaging technique, since pads are distributed around chips, the pads can be connected to a controller through wire bonding, so as to achieve a purpose of arbitrarily selecting a stacked chip. The 3D connection technique generally uses a through silicon via (TSV) connection technique. However, the pads of the TSV connection technique are distributed inside the chips, when the controller wants to control a remote chip of a non-adjacent layer, the controller has to communicate with the remote chip through the TSVs there between, so that the method of directly connecting the controller through the wire bonding approach may result in a fact that the chips closer to the controller have to spend more area on TSVs, so as to provide a communication usage for the remote chips, which may spend a great overhead for stacking the same chips.
In issued or published patents, the memory stacking techniques using the TSV connection technique are approximately divided into two main types of a decoded chip select signal and an encoded chip select signal according to control signals for chip selection. The decoded chip select signals are generated by the controller, and a plurality of the generated select signals is transmitted to the chip of each layer n a one-to-one mode, so that a number of the select signals represent a maximum number of the memory chips capable of being stacked. Regarding the encoded chip select signal, the encoded select signal is generated by the controller, and the same select signal is transmitted to the chip of each layer through the TSVs. The chip of each layer compares the select signal with a unique identification (ID) code defined in the chip to determine whether or not to activate a related operation. After the chip stacking is completed, the ID codes are unchangeable, while the select signal is changeable. For example, a first ID code is built in a first chip, and a second ID code is built in a second chip, where the first ID code is different to the second ID code. The controller generates the select signal to the first chip and the second chip, where if the select signal is complied with the first ID code, the first chip is activated, and if the select signal is complied with the second ID code, the second chip is activated.
However, in the conventional technique, some processes are required to make all identical chips to be identifiable to each other (for example, a fuse-programmable method is used to program the unique ID code in the identical chip of each layer), so that cost of staking the chips is increased. Alternatively, a logic circuit is used to generate the unique code for each of the stacked chips for comparing with the select signal, though according to such method, hardware cost is still increased. For example, regarding 3D memory stacking using the TSV connection technique, the memory chip of each layer has completely identical circuit structure, layout and connection, so that positions of the TSVs of the memory chip of each layer are identical. Therefore, how to generate logic differences capable of being identified for the 3D memory stacking is an issue to be developed in the 3D stacking technique for various manufactures.